1. Field of the Invention
The field of the invention relates to data processing and in particular to maintaining memory coherency in a data processing apparatus having multiple masters, at least one local cache and a memory.
2. Description of the Prior Art
FIG. 1 shows schematically a very simple system where coherency problems can arise. This system has a DMA 5 (direct memory access device) that accesses a memory 25 via a bus 20. There is also a processor CPU 10 that has a local cache and that also accesses the memory 25. In this example the cache of the CPU 10 is configured as a write-through cache so that data that the CPU 10 writes to the memory is written to the cache as well. This allows the CPU 10 to access this data more quickly later. However, as the DMA 5 is also accessing the memory 25 it may overwrite a data item stored in the memory that is also stored in the cache of the CPU. This would result in the CPU 10 storing an out of date value for that data item which if not corrected could result in errors in the CPU's processing. To protect against this there is a monitoring circuit 12 provided that snoops writes sent from the DMA 5 on the bus 20 and in response to detecting a write to an address stored in the cache of CPU 10 it invalidates the line in the cache storing this value. This means that a future access to the data item by the CPU 10 will miss in the cache and the CPU will access the memory 25 and retrieve the correct value. A problem with this system is that snooping of the bus and invalidation of the line in the cache takes time and in order to avoid errors it must happen quickly enough to keep up with the DMA writes, otherwise if an interrupt occurs between the DMA 5 updating a value of a data item in the memory and the corresponding cache line being invalidated an incorrect value could be stored in the CPU.
One way of addressing this problem is to put “back pressure” on the DMA so that it is stalled until the CPU has completed its work on the cache. FIG. 2 shows an example of a system having a write-back cache where the CPU 30 writes a data value to its cache and marks it as dirty and updates the memory and then marks the value as clean. This increases the speed of the writes but makes the coherency scheme more complex. In such a system, the most up to date value of a data item may be stored in the cache and not in the memory and thus, the snoop unit blocks any DMA writes if it detects the value to be stored in the CPU until the cache has been invalidated and cleaned if required. This maintains coherency but introduces significant delays as the DMA writes are stalled until the CPU has done the required work on its cache.
It would be desirable to be able to maintain cache coherency without unduly increasing processing delays.